Years of Working: 1-3 Years

1. According to requirements, complete the DFT design scheme of the chip;

2. Responsible for the realization of DFT functions such as SCAN, MBIST, Boundary SCAN, Hard Macro Test;

3. Responsible for DFT timing constraints and optimization convergence;

4. Responsible for DFT test pattern generation and coverage improvement;

5. Responsible for testing pattern debugging, testing time optimization and yield improvement.

1.Bachelor’s degree or above. Major in computer, microelectronics, circuit and system chip design;

2. Familiar with the DFT development process, with rich experience in DFT such as SCAN, MBIST, Boundary SCAN, Hard Macro Test;

3. Familiar with the use of common DFT tools such as DFT Compiler, DFTMax, TetraMax, TestKompress, Tessent MBist;

4. Rich experience in DFT timing optimization, test pattern generation, test pattern debugging, test time optimization and yield improvement;

5. Experience in DFT design of mobile phones, IPC, ADAS, AI and other chips is preferred.

Department: Human Resources Administration Department 

Education: Bachelor   

Years of working: 5-10 years 

1. Responsible for the company to formulate relevant systems, processes and norms for salary management, benefit management, etc., and optimize and adjust;
2. Prepare salary table to ensure the timely and correct issuance of monthly company labor costs;
3. Investigate and understand the salary policy and salary level of each region where the company is located, and provide a basis for the company’s decision-making;
4. Responsible for employee policy consultation, adjust and plan welfare projects in a timely manner based on employee feedback;
5. Assist in handling employee relationship maintenance;
6. Participate in the formulation of appropriate personnel policies to support business development;
7. Support other HR aspects of work.

1. Bachelor degree or above, majors in human resource management, business management and other related majors are preferred;
2. CET-4, human resources qualification certificate is preferred;
3. More than 8 years of human resources work experience, at least 5 years of practical operation experience of salary and benefits;
4. Familiar with policies, regulations and processes of labor, wages, insurance, personal income tax and social insurance benefits;
5. Have good data analysis ability, analysis and prediction ability;
6. Strong logic, careful work, patient, cheerful personality.

Department: System & Software R&D Department  

Education: Undergraduate  

Years of working: 1-3 Years  

1. Responsible for the daily maintenance and management of computer software and hardware;
2. Responsible for the daily maintenance and management of the company’s network and office equipment;
3. Collect and sort out user IT requirements;
4. Maintenance and management of common IT application services;
5. Participate in IT project related work;
6. Complete other daily IT related work arranged by superiors.

1. Bachelor degree, computer related major;
2. CET-4, good reading comprehension ability of English technical materials;
3. Familiar with common computer software and hardware troubleshooting;
4. Familiar with the use of common office equipment and software;
5. Familiar with common network protocols, familiar with common network equipment;
6. Understand the Linux operating system and common Linux application services;
7. Familiarity with at least one scripting language;
8. Strong learning ability, communication ability, teamwork ability, active service consciousness.

Department: System & Software R&D Department  

Education: Undergraduate  

Years of working: 3-5 Years  

1. Construction of RISCV CPU development environment;
2. Continuous integration of RISCV CPU verification platform.

1. Full-time undergraduate degree or above, more than 2 years of relevant development experience;
2. Proficient in using Python;
3. Proficient in using Linux Shell;
4. Good document writing and communication skills;
5. Learning ability, work attitude, sense of responsibility.

Department: Computer IP R&D Department

Education: Undergraduate

Years of Working: 1-3 Years

As a member of SpacemiT’s NPU architecture and development team, you will participate in the modeling, micro-architecture design and implementation of self-developed NPU IP suitable for various Edge devices. 

1. Combined with the application of AI algorithms in edge-side image, video, human-computer interaction, IoT and other fields, explore the best implementation of general-purpose NPU that meets the computing power, data bandwidth and delay requirements of various algorithms;
2. Be responsible for innovating, optimizing and designing the instruction mapping, task scheduling, memory access method and storage structure of AI algorithm on NPU through AI algorithm modeling, simulation and result analysis;
3. Responsible for the micro-architecture definition and RTL design of each sub-module of SpacemiT’s NPU, and participate in the complete process from micro-architecture to RTL-level implementation;
4. Improve the power consumption, performance and area (PPA) indicators of various AI algorithms on the progressive space-time NPU.

1. Computer system structure, major in computer, microelectronics, circuits and systems, communication, artificial intelligence, etc., with solid theoretical foundation in computer architecture or microelectronics, with certain engineering and coding capabilities, as well as research and innovation capabilities;
2. Familiar with mainstream AI algorithms or deep learning frameworks, AI performance analysis and tuning of CPU/GPU/DSP, relevant experience is preferred;
3. Familiar with Gem5 or other micro-architecture simulators, experience in modeling and simulation is preferred;
4. Familiar with hardware module design (Verilog, System Verilog, Chisel, etc.), experience in GPU, NPU, DSP processor design or verification is preferred.

Department: Computer IP R&D Department  

Education: Master  

Years of working: Unlimited  

As a member of the SpacemiT team, you will be responsible for logic design and verification within digital integrated circuits. 

1. Microelectronics, computer, communication engineering, automation, electromagnetic field and other related majors;
2. Those who meet any of the following conditions are preferred:

-Familiar with VHDL/Verilog, SV and other digital chip design and verification languages, and participated in FPGA design or verification;

-Experience in digital chip synthesis (SYN)/timing analysis (STA);

-Understand the basic knowledge of chip design, such as code specifications, working environment and tools, typical circuits (asynchronous, state machine, FIFO, clock reset, memory, cache management, etc.);

-Have been exposed to a variety of verification tools, understand one or more verification methods, and formulate different verification strategies and schemes according to the characteristics of the project, build a verification environment, and complete verification execution and debugging.

As a member of the SpacemiT team, you will be responsible for logic design and verification within digital integrated circuits. 

1. Microelectronics, computer, communication engineering, automation, electromagnetic field and other related majors;
2. Those who meet any of the following conditions are preferred:

A.Familiar with VHDL/Verilog, SV and other digital chip design and verification languages, and participated in FPGA design or verification;

B.Experience in digital chip synthesis (SYN)/timing analysis (STA);

C.Understand the basic knowledge of chip design, such as code specifications, working environment and tools, typical circuits (asynchronous, state machine, FIFO, clock reset, memory, cache management, etc.);

D.Have been exposed to a variety of verification tools, understand one or more verification methods, and formulate different verification strategies and schemes according to the characteristics of the project, build a verification environment, and complete verification execution and debugging.

Department: SoC R&D Department  

Education: Undergraduate  

Years of working: 1-3 Years  

1. Responsible for the SoC verification of the chip;
2. Read the relevant design documents, understand the design requirements and define the test plan;
3. Build module-level and SoC-level verification environments to generate test vectors;
4. Execute the test plan and perform coverage analysis;
5. Define, generate and analyze various verification indicators;
6. Perform gate-level simulation and emulation;
7. Pay attention to the development of mainstream verification technologies, introduce advanced verification technologies and strategies, and improve the quality and efficiency of verification.

1. Bachelor degree or above, major in electronic engineering, communication, computer is preferred;

2. Proficient in system verilog; and UVM methodology, able to independently build a module/SOC verification environment;

3. The following work experience is preferred:

-CPU, Video/Audio Codec, ISP, Security IP, NPU and other verification experience;

-Hardware accelerator or emulator experience;

-Validation process/tool development;

-ASIC design experience.

4. Master at least one scripting language: Perl, Shell, Ruby, Python, Tcl, etc.;

5. Passionate, self-driven, good teamwork spirit;

6. Good communication and expression skills and problem analysis skills.

Department: Computer IP R&D Department  

Education: Undergraduate  

Years of working: 1-3 Years  

1. According to the requirements, complete the spec formulation, code writing and integration of modules/subsystems/systems;
2. Assist in verification, synthesis, DFT, FPGA, back-end, driver, testing, software development, etc.;
3. Optimize and improve the design according to feedback from personnel in various fields such as verification, synthesis, DFT, FPGA, back-end, software, and systems;
4. Analyze various indicators such as bandwidth, area, performance, power consumption, etc. to ensure that the design requirements are met, and continue to iteratively optimize.

1. Major in chip design related to computer, microelectronics, circuit and system;
2. Familiar with the SoC development process, with rich experience in code writing, simulation and debugging;
3. Familiar with AHB, AXI and other bus protocols, those with NoC experience are preferred;
4. Proficient in one or more of the following IPs: DDR, PCIe, USB, Ethernet, UFS, Emmc, etc.;
5. Rich experience in system integration, chip design experience in mobile phone, IPC, ADAS, AI, etc. is preferred.

Department: SoC R&D Department  

Education: Undergraduate  

Years of working: 1-3 Years  

As a member of SpacemiT’s SoC architecture and development team, you will be involved in the modeling, architecture design and implementation of SoCs for each product line. 

1. Participate in the implementation of specific SoC chip solutions from application and product definition, and be responsible for defining the latest SoC chip architecture;
2. Responsible for SoC chip modeling, performance analysis and low-power design, as well as the selection and demand analysis of each sub-module, including RISC-V processor core, NPU, GPU, on-chip bus, storage interface, etc., overall chip solution competitiveness;
3. Responsible for the integration of the space-time SoC chip, and participate in the complete process from micro-architecture to RTL-level implementation.

1. Computer system structure, major in computer, microelectronics, circuits and systems, communication, artificial intelligence, etc., with solid theoretical foundation in computer architecture or microelectronics, with certain engineering capabilities and coding capabilities, as well as research and innovation capabilities ;
2. Familiar with on-chip interconnection NoC technology, IO interface protocols (DRAM, MIPI, PCIE) and hybrid memory system principles commonly used in the industry, and relevant IP experience is preferred;
3. Familiar with the entire design process of SoC chips, practical project experience is preferred;
4. Familiar with the common low-power design verification process in the industry, experience is preferred.

As a member of SpacemiT’s SoC architecture and development team, you will be involved in the modeling, architecture design and implementation of SoCs for each product line. 

1. Participate in the implementation of specific SoC chip solutions from application and product definition, and be responsible for defining the latest SoC chip architecture;
2. Responsible for SoC chip modeling, performance analysis and low-power design, as well as the selection and demand analysis of each sub-module, including RISC-V processor core, NPU, GPU, on-chip bus, storage interface, etc., overall chip solution competitiveness;
3. Responsible for the integration of the space-time SoC chip, and participate in the complete process from micro-architecture to RTL-level implementation.

1. Computer system structure, major in computer, microelectronics, circuits and systems, communication, artificial intelligence, etc., with solid theoretical foundation in computer architecture or microelectronics, with certain engineering capabilities and coding capabilities, as well as research and innovation capabilities ;
2. Familiar with on-chip interconnection NoC technology, IO interface protocols (DRAM, MIPI, PCIE) and hybrid memory system principles commonly used in the industry, and relevant IP experience is preferred;
3. Familiar with the entire design process of SoC chips, practical project experience is preferred;
4. Familiar with the common low-power design verification process in the industry, experience is preferred.

Department: Computer IP R&D Department  

Education: Undergraduate  

Years of working: 1-3 Years  

1. Participate in the verification of 32/64-bit high-performance CPUs for various application fields;
2. Work closely with the design team to formulate verification plans, write test cases, and debug;
3. Collection and analysis of functional coverage, enhanced test set to solve coverage loopholes;
4. Explore processor verification methodology, participate in the construction of processor verification environment, develop verification tools, and learn cutting-edge technologies in related fields.

1. Bachelor degree or above, major in electronic engineering, communication, computer is preferred;
2. Familiar with RISC-V architecture;
3. Familiar with processor architecture, including pipeline, branch prediction, out-of-order execution, cache, multi-core consistency;
4. Proficient in the verification process driven by functional coverage;
5. Proficient in UVM verification methodology and have a deep understanding of restricted random testing;
6. Familiar with digital circuit design process;
7. The following work experience is preferred:

-Participated in specific CPU verification;

-Participated in processor reference model development;

-Proficient in assembly language writing;

-Proficient in verilog/system verilog;

-Proficient in scripting languages such as perl/tcl;

-Proficient in programming languages such as C/C++.

Department: SoC R&D Department 

Education: Bachelor 

Years of working: 5-10 years 

1. Responsible for the design and verification of system hardware solutions in the process of chip research and development, including but not limited to competitive product analysis, system hardware architecture design, subsystem design, chip bring-up verification board development and debugging, and analyzing problems found in chip verification and providing solutions Program; 
2. Responsible for chip reference design board design and output, and provide technical support for customers; 
3. Participate in chip design, from the perspective of system design and debugging, including but not limited to the definition of key specifications such as chip function and performance; 
4. Continue to track the development trend in the field of system hardware development in the industry and promote the commercialization of related technologies. 

1.Communication, electronics, computer and other related majors, rich experience in system hardware architecture design and ability to implement, proficient in analog-electrical, digital-electrical theoretical knowledge and underlying hardware interface protocols, as well as the characteristics and usage of common electronic components; 

2.Proficient in one or more of the following system hardware design and tuning capabilities: 

-High-speed signal: LPDDR4/4X, MIPI, USB3.0, etc.; 

-Audio and video: Codec, Camera, Sensor, LCD, etc.; 

-Reliability: ESD/EMI; 

-Power system: PMIC, DCDC, etc. design; 

3.Proficient in EDA tools such as Cadence/PADS; 

4.Strong logical thinking ability, problem analysis ability, communication ability, learning ability and teamwork awareness; 

5.C and other programming language ability is preferred. 

Department: SoC R&D Department 

Education: Bachelor 

Years of working: 5-10 years 

1. Responsible for developing test program, test methods, processes and test plans to accelerate the energy efficiency of chip verification; 
2. Tuning various performance indicators of the chip, including but not limited to clock PLL, high-speed interface, low-speed interface, various static and dynamic power consumption, various digital functions, images, high-precision ADC, audio and video, etc.; 
3. Responsible for formulating chip reliability plans, including but not limited to stress testing, four-corner deflection testing, etc.; 
4. Responsible for analyzing test data, aligning ATE characterization data and front-end simulation data, improving test stability, and assisting designers in tracking abnormalities; 
5. Responsible for the description of the chip electrical characteristics manual, and provide corresponding technical support for customers; 

1.More than 5 years of original chip evaluation and testing work, proficient in testing theoretical knowledge and procedures, proficient in the use of various testing instruments, including but not limited to high-speed oscilloscopes, bit error detectors, power analyzers, logic analyzers, network analyzers, etc.; 

2.Proficient in one or more of the following chip test solutions and methods to achieve industry-leading: 

-High-speed interface: PCIE, MIPI, HDMI, DP, USB3.0, etc. 

-DDR4, LPDDR4/4X, DDR5; 

-Image IPS etc. 

-Static\dynamic power consumption, etc.; 

-High-precision analog: ADC\DAC\power system, etc.; 

-Reliability; 

-Audio and video: codec, ISP, etc.; 

3.Strong logical thinking ability, problem analysis ability, communication ability, learning ability and teamwork awareness; 

4.Experience in automated chip platform is preferred; 

5.C, C#, Python and other programming languages ​​are preferred. 

Department: SoC R&D Department 

Education: Bachelor 

Years of working: 5-10 years 

1. Responsible for the selection and development of chip packaging solutions: 
2. Responsible for chip ball map arrangement and substrate design; 
3. Responsible for the simulation review of chip packaging SI, PI, thermal and stress; 
4. Responsible for manufacturing and yield improvement in cooperation with foundry, PE, QA, and other departments. 

1. Bachelor or master’s degree in electronic engineering or other related majors, more than 5 years’ experience in large chip packaging;
2. Experience in high-speed IO interface design, including but not limited to DDR, PCIE, etc.;
3. Experience in design of oversized flip-chip packages and knowledge of thermal and stress reliability;
4. Have an in-depth understanding of the development direction of chip packaging design related technologies, and have a certain outsourced factory management experience;
5. Strong logical thinking ability, problem analysis ability, communication ability, learning ability and teamwork awareness.

Department: SoC R&D Department 

Education: Bachelor 

Years of working: 5-10 years 

1. Responsible for package and board level SI, PI modeling and simulation; 

1. Responsible for the establishment of SI and PI processes and the development of methodology; 

1. Responsible for providing detailed SI and PI design rules for package and board level engineering; 

1. Responsible for outputting ibis mode and PDN, and providing corresponding technical support for customers. 

1. Related background of EE/ME/CS system chip, more than 5 years of high-speed digital design experience: 

1. Familiar with SI\PI analysis process, system-level modeling and EDA analysis tools (HFSS/ADS/Spice/Allegro, etc.); 

1. High-speed packaging and system design experience (DDR\PCIE, etc.); 

1. Familiar with Perl/TCL scripts in Linux/Unix environment, C language is preferred; 

1. Strong logical thinking ability, problem analysis ability, communication ability, learning ability and teamwork awareness. 

Years of working: 1-3 years 

Education requirements: Bachelor degree or above 

1. Bachelor’s degree or above in computer, electronic engineering and related majors;
2. More than 2 years of C/C++ development experience;
3. Understand common computer architectures not limited to CPU, GPU, etc.

1. Work experience in AI/robotics field, good mathematical skills, familiar with neural network, machine vision, SLAM and other algorithm principles;
2. Experience in AI operator optimization and high-performance software development including but not limited to SIMD, VLIW, SIMT related optimizations;
3. Experience in TVM, MLIR pass and other development;
4. Familiar with software development tools and scripting languages, including but not limited to Git, CMake, Python, Perl, etc.
5. Familiar with the design and implementation of unit test cases, CI/CD, etc.

Department: Computer IP R&D Department  

Education: Undergraduate  

Years of working: 1-3 Years  

As a member of SpacemiT’s CPU architecture and development team, you will participate in the modeling, micro-architecture design and implementation of self-developed RISC-V processor cores for various application scenarios. 

1. Explore the most cutting-edge RISC-V development and trends, including the progress of the RVI community, achievements in academia and industry, changes and trends in customer needs, and excellent engineering practices in the industry;
2. Research and summarize the characteristics of mainstream applications and benchmark programs, analyze the key factors of performance bottlenecks through modeling, simulation and prototype verification, and lead the innovation, optimization and design of micro-architecture;
3. Responsible for the micro-architecture definition and RTL design of the new features of SpacemiT’s RISC-V processor core, and participate in the complete process from micro-architecture to RTL-level implementation;
4. Improve the power, performance and area (PPA) metrics of SpacemiT’s RISC-V processor cores.

1. Computer system structure, major in computer, microelectronics, circuits and systems, communication, artificial intelligence, etc., with solid theoretical foundation in computer architecture or microelectronics, with certain engineering and coding capabilities, as well as research and innovation capabilities;
2. Familiar with RISC-V (or Arm) general-purpose processor instruction set and micro-architecture, Cache algorithm and micro-architecture, branch prediction algorithm and micro-architecture, etc., relevant experience is preferred;
3. Familiar with on-chip interconnection NoC technology and inter-chip interconnection protocols commonly used in the industry, have certain research on storage media, and be familiar with the principle, structure and data consistency of multi-core processor Cache;
4. Familiar with Gem5 or other micro-architecture simulators, experience in modeling and simulation is preferred;
5. Familiar with the design of hardware modules (Verilog, SystemVerilog, Chisel, etc.), experience in CPU or DSP processor design or verification is preferred.

Soft Skills : Curiosity drives exploration, good innovation ability, pursuit of work to the extreme, good teamwork ability.